International Journal of Advances in Engineering & Scientific Research

International Journal of Advances in Engineering & Scientific Research

Print ISSN : 2349 –4824

Online ISSN : 2349 –3607

Frequency : Continuous

Current Issue : Volume 1 , Issue 6
2014

IMPLEMENTATION OF A 8 BIT HIGH PERFORMANCE MULTIPLIER USING HDL

*Ch. Praveen Kumar, **K. Praveen Kumar

*Department of ECE GITAM University,  Hyderbad, Telangana, India,    **Department of ECE GITAM University, Hyderbad Telangana, India

DOI : Page No : 23-30

Published Online : 2014-10-30

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Abstract

This paper presents an area efficient implementation of a 8 bit high performance parallel multiplier.  Radix-8  Booth  multiplier  with  carry  look ahead adder and modified carry look ahead adder are presented here. The design is structured for 8   bit multiplication. Carry Look ahead Adder is used as the final adder to enhance the speed of operation. Finally the performance improvement of the proposed multipliers is validated  by  implementing  a  multiplier  with  modified carry  look  ahead  adder.  The  design  entry  is  done  in Verilog and simulated using Model Sim SE 6.4 design suite from Mentor Graphics. It is then synthesized and implemented using Xilinx ISE 9.2i .

 

Keywords- HDL; Modified Carry Look-ahead Adder; Carry Save Adder; Wallace Tree; Booth Encoding

Int. J. of Adv. in Engg. & Sci. Res.